As MOSFET and CMOS device characteristic sizes are scaled down to below 0.25 microns including below 0.1 microns, the process window for dry etching processes is increasingly difficult to control. For example, a fine balance between an etching rate and an etching selectivity to underlying materials is increasingly difficult to control given the limited range within which a particular etching process may be varied in etching ultra-thin dielectric films.
Increasingly with smaller device sizes, it is necessary to etch through a thickness of a thin film of material, for example less than about 100 Angstroms without causing etching damage to an underlying material layer. Perhaps most critical, are etching processes to remove material layers overlying semiconductor substrate portions such as the source and drain regions as well as removing material overlying or adjacent to polysilicon gate electrodes.
Several approaches to improve dry etching processes have included using polymer forming fluorocarbon, fluorohydrocarbon, and perfluorocarbon containing etching chemistries. The general concept is that, depending on the etching chemistry, a polymer layer is formed from the etching chemistry constituents to create a covering over portions of the etching surface thereby controlling an etching rate and anisotropicity. A problem with this approach has been the high RF powers required to sufficiently dissociate the etching chemistry constituent to form the polymer layer which additionally increases the etching rate thereby making the controlled etching of thin layers more difficult to control. On the other hand, reducing RF power to reduce the etching rate causes poor selectivity and deteriorates etching uniformity.
One particular problematic area where the etching of thin layers has created a problem is in the formation of sidewall spacer dielectrics, also referred to as offset spacer dielectrics, formed adjacent to the gate structure. The sidewall spacer dielectric formed adjacent either side of the gate structure serves to allow source/drain extensions (SDE) to be formed whereby a relatively lower amount of N or P-type doping is first formed in the semiconductor substrate adjacent the gate structure by ion implantation prior to forming the sidewall spacers which then act as an ion implant mask for forming higher doped regions adjacent the sidewall spacers.
As device characteristic dimensions shrink below about 0.25 microns including below about 0.1 micron, achieving close dimensional tolerances of sidewall spacers is critical to achieving reliable electric performance and avoiding short channel effects (SCE). For example, SDE regions affect SCE according to both depth and width of the SDE doped region. The formation of sidewall spacers typically requires dry etching processes to remove portions of the sidewall spacer dielectric layer overlying a different material such as an oxide or silicon where overetching can degrade device performance or require additional processing steps to repair the damage.
There is therefore a continuing need in the semiconductor integrated circuit manufacturing art for improved dry etching processes for thin film dielectrics whereby a process control window is improved including achieving a higher etching selectivity to underlying layers as well as avoiding unintentional overetching of thin dielectric layers.
It is therefore among the objects of the present invention to provide improved dry etching processes for thin film dielectrics whereby a process control window is improved including achieving a higher etching selectivity to underlying layers as well as avoiding unintentional etching and damage to underlying layers, in addition to overcoming other shortcomings of the prior art.